In the fabrication of integrated circuits it is often necessary to form a large number of transistors on a single chip. These transistors are interconnected to form logic gates, flip-flops, memory cells and a wide variety of other devices. A gate array is an array of transistor circuits which utilize the same base cell for many different applications. In this configuration, only the final interconnect levels of the multilevel device are specifically designed for any given application. The initial levels, known as the base cell, are the same for each implementation. In typical applications the base cell includes a heavily doped moat region separated by lightly doped channel region and a gate insulatively overlying the channel region.
One type of gate array includes moat regions which comprise p-doped silicon and other moat regions which comprise n-doped silicon. These regions can be used to create p-channel and n-channel devices, respectively. One example of an application which uses both conductivity type channels is a CMOS (complementary metal oxide semiconductor) device.
Many gate array applications require the gates of adjacent base cells to be connected electrically. This electrical connection is often made when the gates are formed during the base cell fabrication. Connected gates are common in CMOS devices such as inverters or NAND gates, for example.
In other applications, such as single or complementary transfer gates or some dynamic circuits for example, however, it is inefficient to "pre-connect" (i.e., connect during base cell fabrication) the gates of adjacent cells.
To solve the problem of having both gates that are connected and gates that are not connected, the entire base cell may be redesigned for each application. This custom design approach, however, is costly because more levels of the multilevel fabrication must be built for each specific application.
Another solution is to either connect all cell gate pairs or leave all cell gate pairs disconnected. This solution, however, leads to inefficient base cell usage.
Accordingly, improvements which overcome any or all of the problems are presently desirable.